FIG. 1 shows a block diagram of a multi-port memory device 100 including a first port 102, a second port 104, a memory core 105, and an authority controller 107. The memory core 105 includes an array of memory cells that are organized into a first memory bank 106, a second memory bank 108, a third memory bank 110, and a fourth memory bank 112.
The first memory bank 106 is dedicated for access just by a first data processor 113 via the first port 102. The third and fourth memory banks 110 and 112 are dedicated for access just by a second data processor 115 via the second port 104. The second memory bank 108 has shared access by the first and second data processors 113 and 115 via the first and second ports 102 and 104, respectively.
Just one of the ports 102 and 104 has access to the shared memory bank 108 at any given time. The access controller 107 arbitrates access to the shared memory bank 108 between the ports 102 and 104. On the other hand, the first port 102 has access to its dedicated bank, i.e., the first memory bank 106, at any time. Similarly, the second port 104 has access to its dedicated banks, i.e., the third and fourth memory banks 110 and 112, at any time.
FIG. 2A illustrates the memory banks 106, 108, 110, and 112 when the memory core 105 is for 512 Mb (Mega-bit) memory capacity, according to the prior art. In that case, each of the memory banks 106, 108, 110, and 112 is for 128 Mb. FIG. 2B illustrates the memory banks 106, 108, 110, and 112 when the memory core 105 is for 1.024 Gb (Giga-bit) memory capacity, according to the prior art. In that case, each of the memory banks 106, 108, 110, and 112 is for 256 Mb. In FIGS. 2A and 2B, each of the memory banks 106, 108, 110, and 112 has same memory capacity in the memory core 105.
In the prior art of FIGS. 2A and 2B, each of the first and second data processors 113 and 115 uses a same addressing scheme with a same memory capacity per bank for accessing the memory core 105. Thus, a similar number and configuration of addressing bits are used by the first and second data processors 113 and 115 for accessing the memory core 105 in the prior art. For example, a similar number and position of bits for specifying bank and row addresses of the memory core 105 are used by the first and second data processors 113 and 115 in the prior art.
However, more flexibility may be desired for addressing the memory core 105 by the first and second data processors 113 and 115 in a multi-port memory device. In addition, routing access to the memory core 105 by the first and second data processors 113 and 115 with minimized bus area is desired in a multi-port memory device.